1. Field of the Invention
The present invention relates to a semiconductor device formed using a single crystal silicon substrate, and in particular to the structure of an insulated gate field effect transistor (called “MOSFET” or “IGFET”). More particularly, the present invention relates to a technique by which an effect is exhibited in the case where a fine element whose channel length is 0.3 μm or less (representatively 0.05 to 0.2 μm) is manufactured. Also, the present invention is applicable to various semiconductor circuits such as an IC, a VLSI or a ULSI which is structured with an integrated MOSFET.
2. Description of the Related Art
A MOSFET changes the potential of a semiconductor (representatively silicon) interface just under a gate by a gate voltage to on/off-control electron flow or hole flow between a source and a drain.
However, as the channel length of the transistor is made shorter, the source comes in contact with a space-charge region (also called “depletion layer”) in the vicinity of the drain. In this situation, although the potential of the semiconductor interface close to the gate is controllable by the gate potential, a potential of a portion deeper from the gate remains high even if the gate voltage is dropped because it is influenced by the drain voltage.
That is, even if the gate voltage is set as 0 V in order to turn off the transistor, a leakage current is allowed to flow through a portion of the semiconductor substrate which is high in potential (a portion where the space-charge region is widened). This is called “short-channel effect” and appears as a phenomenon such as an increase in S value (sub-threshold coefficient) or a drop of a threshold voltage.
As a phenomenon in which the degree of the short-channel effect is large, there occurs punch-through where a current remains flowing. The fined MOSFET is advantageous in low voltage and high speed. In order to succeed in obtaining those advantages, it is essential to restrain the short-channel effect and reduce an on-state resistance.
In order to fine the MOSFET while the short-channel effect is restrained, a scaling method has been proposed by Dennard in 1974. In order to shorten the gate length as the short-channel effect is restrained through this method, the following means are effective.
(1) A gate insulating film is thinned.
(2) A junction depth of a source and a drain is thinned.
(3) The space-charge region width (depletion layer width) is restrained.
As to the means (1), the limited thickness of the gate insulating film is 3 nm at presence. Also, as to the means (2) with respect to the junction depth, although a study is made to devise an ion doping apparatus or to conduct laser doping, there remain various problems in the case of the deep sub-micron size or lower.
The method of (3) is to increase the concentration of the channel forming region as first proposed, that is, channel doping. However, in the formation of the MOSFET with fine dimensions such as 0.18 μm rule, it is necessary to add impurities of about 1×1018 atoms/cm3. This causes an on-state current to be remarkably lowered.
As another method, there is proposed a method called “Double implanted LDD” as shown in FIG. 2A. This is of the structure in which slightly weak p-type (p-) regions 203 and 204 are disposed just under n-regions (LDD regions) 201 and 202 or so as to surround those n-regions (LDD regions) 201 and 202 by implanting ions. In particular, in the case where those p-type (p-) regions 203 and 204 are disposed so as to surround the LDD region, it may be called “pocket structure”.
In addition, there has been proposed a punch-through stopper structure (FIG. 2B) in which a p-type region (p-region) 206 high in concentration is formed by the substrate in the interior of the substrate at a channel portion. All of those methods are of engineering in a depthwise direction of the substrate or in a direction of the gate (channel) length.
However, the structures mentioned in the above-described conventional examples as shown in FIGS. 2A and 2B suffer from several problems. Because the structure shown in FIG. 2A is of the structure in which the p-region is disposed just under the drain region (also including the LDD region), the effect of restraining the short-channel effect cannot be expected so much.
Also, the type called “pocket structure” suffers from such a problem that the mobility is deteriorated since carriers (exemplified by electrons) always pass through the p-region before they reach the drain region.
Further, the structure shown in FIG. 2B is designed to control the concentration in the depthwise direction by through-doping after a gate electrode is formed as usual. Accordingly, the structure is not preferable in order to enhance the mobility because the crystallinity of the semiconductor layer interface is destroyed in addition that the control of the concentration distribution is very difficult.